Hardware acceleration architectures for MPEG-Based mobile video platforms: a brief overview

This paper presents a brief overview of past and current hardware acceleration (HwA) approaches that have been proposed for the most computationally intensive compression tools of the MPEG-4 standard. These approaches are classified based on their historical evolution and architectural approach. An analysis of both evolutionary and functional classifications is carried out in order to speculate on the possible trends of the HwA architectures to be employed in mobile video platforms.

[1]  Noel Brady MPEG-4 standardized methods for the compression of arbitrarily shaped video objects , 1999, IEEE Trans. Circuits Syst. Video Technol..

[2]  Hsueh-Ming Hang,et al.  A comparison of block-matching algorithms mapped to systolic-array implementation , 1997, IEEE Trans. Circuits Syst. Video Technol..

[3]  Wen-Hsiung Chen,et al.  A Fast Computational Algorithm for the Discrete Cosine Transform , 1977, IEEE Trans. Commun..

[4]  Aggelos K. Katsaggelos,et al.  MPEG-4 and rate-distortion-based shape-coding techniques , 1998, Proc. IEEE.

[5]  Sethuraman Panchanathan,et al.  Motion estimation architecture for video compression , 1993 .

[6]  Jaakko Astola,et al.  Architecture-oriented regular algorithms for discrete sine and cosine transforms , 1999, IEEE Trans. Signal Process..

[7]  A. Chandrakasan,et al.  A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization , 1999, IEEE Journal of Solid-State Circuits.

[8]  Chi-Ying Tsui,et al.  Low-power VLSI design for motion estimation using adaptive pixel truncation , 2000, IEEE Trans. Circuits Syst. Video Technol..

[9]  Thomas Sikora,et al.  Shape-adaptive DCT for generic coding of video , 1995, IEEE Trans. Circuits Syst. Video Technol..

[10]  Liang-Gee Chen,et al.  An efficient and simple VLSI tree architecture for motion estimation algorithms , 1993, IEEE Trans. Signal Process..

[11]  Peter Pirsch,et al.  Multicore system-on-chip architecture for MPEG-4 streaming video , 2002, IEEE Trans. Circuits Syst. Video Technol..

[12]  Liang-Gee Chen,et al.  VLSI architecture design of MPEG-4 shape coding , 2002, IEEE Trans. Circuits Syst. Video Technol..

[13]  Tihao Chiang,et al.  A novel all-binary motion estimation (ABME) with optimized hardware architectures , 2002, IEEE Trans. Circuits Syst. Video Technol..

[14]  Yeong-Kang Lai,et al.  A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm , 1998, IEEE Trans. Circuits Syst. Video Technol..

[15]  Peter Pirsch,et al.  VLSI architectures for video compression-a survey , 1995, Proc. IEEE.

[16]  Peter Kuhn,et al.  Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation , 1999, Springer US.

[17]  Kenneth Y. Yun,et al.  A low-power VLSI architecture for full-search block-matching motion estimation , 1998, IEEE Trans. Circuits Syst. Video Technol..

[18]  Dong Sam Ha,et al.  On the low-power design of DCT and IDCT for low bit-rate video codecs , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[19]  Manfred Glesner,et al.  Flexible architectures for DCT of variable-length targeting shape-adaptive transform , 2000, IEEE Trans. Circuits Syst. Video Technol..