A mobile sensor system for very low level biological signals such as neuron spikes is required to implement with a scaled CMOS technology. For a key circuit of these systems, a chopper amplifier (CA) which suppresses DC offset and 1/f noise of MOS devices is widely used. However, the conventional CA consumes large power because it requires a wide-band amplifier exceed a chopping frequency and a post Low Pass Filter (LPF) for eliminating modulation noise. In this paper, a new CA architecture for reducing power consumption is presented. In the architecture, the demodulator is placed at the input of 2nd stage amplifier and the 2nd stage has a narrow band determined with a 1st pole. Moreover the post LPF is not required. The proposed CA was designed and simulated with a 0.18µm CMOS process and a 1.2V supply. When the ratio of chopping frequency and signal band width is set to 100 (=10kHz/100Hz), the power consumption of the CA is reduced to 1/88 (=7µW/616µW) compared with the conventional CA.
[1]
A. Iwata,et al.
A 1V supply 50nV//spl radic/Hz noise PSD CMOS amplifier using noise reduction technique of autozeroing and chopper stabilization
,
2005,
Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..
[2]
Takesi Yoshida,et al.
A Design of Neural Signal Sensing LSI with Multi-Input-Channels
,
2004
.
[3]
K.D. Wise.
Wireless implantable microsystems: coming breakthroughs in health care
,
2002,
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[4]
R. F. Wassenaar,et al.
Low-Power Low-Voltage Chopped Amplifier with a New Class AB Output Stage for Mixed Level Applications
,
1998
.