Optimizing the FPGA Implementation of HRT Systems

The availability of programmable hardware devices with high density of logic elements and the possibility of implementing CPUs (called softcores) using a fraction of the FPGA area offers additional flexibility for the implementation of embedded applications with real-time constraints. When implementing functions on such devices, designers can choose between hardware and software. Also, the designer can select the number of CPUs that must be created to best support the execution of the real-time software. In this paper, we define a design optimization procedure for hard real-time systems, in which each functional block can be implemented in HW, using the logic elements available on the FPGA, or in SW, by means of a real-time task executed by a softcore. The optimizer allocates the functions and the softcores such that the HW implemented part is mapped within the area constraints and the software part is allocated so that schedulability can be guaranteed. When feasible solutions exist, the minimum utilization solution is computed

[1]  David A. Kearney,et al.  The Development of an Operating System for Reconfigurable Computing , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[2]  Yoji Kajitani,et al.  VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Yoji Kajitani,et al.  Module placement on BSG-structure and IC layout applications , 1996, ICCAD 1996.

[4]  Sanjoy K. Baruah,et al.  Robustness results concerning EDF scheduling upon uniform multiprocessors , 2002, Proceedings 14th Euromicro Conference on Real-Time Systems. Euromicro RTS 2002.

[5]  Sanjoy K. Baruah,et al.  Static-priority scheduling on multiprocessors , 2001, Proceedings 22nd IEEE Real-Time Systems Symposium (RTSS 2001) (Cat. No.01PR1420).

[6]  Giuseppe Lipari,et al.  Improved schedulability analysis of EDF on multiprocessor platforms , 2005, 17th Euromicro Conference on Real-Time Systems (ECRTS'05).

[7]  R. Otten.  Automatic Floorplan Design , 1982, DAC 1982.

[8]  Daniele Vigo,et al.  Models and Bounds for Two-Dimensional Level Packing Problems , 2004, J. Comb. Optim..

[9]  Yoji Kajitani,et al.  Module placement on BSG-structure and IC layout applications , 1996, Proceedings of International Conference on Computer Aided Design.

[10]  Evangeline F. Y. Young,et al.  How good are slicing floorplans? , 1997, ISPD '97.

[11]  Sudarshan K. Dhall,et al.  On a Real-Time Scheduling Problem , 1978, Oper. Res..

[12]  James W. Layland,et al.  Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.

[13]  Reinhard Männer,et al.  Multitasking on FPGA Coprocessors , 2000, FPL.

[14]  Evangeline F. Y. Young,et al.  Floorplan area minimization using Lagrangian relaxation , 2000, ISPD '00.

[15]  Proceedings of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2007, April 3-6, 2007, Bellevue, Washington, USA , 2007, IEEE Real-Time and Embedded Technology and Applications Symposium.

[16]  Marco Platzner,et al.  Online scheduling for block-partitioned reconfigurable devices , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[17]  Marco Caccamo,et al.  Adaptive Allocation of Software and Hardware Real-Time Tasks for FPGA-based Embedded Systems , 2006, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06).

[18]  Yao-Wen Chang,et al.  B*-Trees: a new representation for non-slicing floorplans , 2000, DAC.

[19]  Sanjoy K. Baruah,et al.  Partitioning real-time tasks among heterogeneous multiprocessors , 2004, International Conference on Parallel Processing, 2004. ICPP 2004..

[20]  Gordon J. Brebner,et al.  The swappable logic unit: a paradigm for virtual hardware , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[21]  Evangeline F. Y. Young,et al.  How good are slicing floorplans? , 1997, Integr..

[22]  Takeshi Yoshimura,et al.  An O-tree representation of non-slicing floorplan and its applications , 1999, DAC '99.

[23]  C. N. Potts,et al.  Analysis of a linear programming heuristic for scheduling unrelated parallel machines , 1985, Discret. Appl. Math..

[24]  Majid Sarrafzadeh,et al.  Fast Template Placement for Reconfigurable Computing Systems , 2000, IEEE Des. Test Comput..

[25]  Jan Karel Lenstra,et al.  Approximation algorithms for scheduling unrelated parallel machines , 1987, 28th Annual Symposium on Foundations of Computer Science (sfcs 1987).

[26]  Andrea Lodi,et al.  Two-dimensional packing problems: A survey , 2002, Eur. J. Oper. Res..

[27]  James H. Anderson,et al.  Early-release fair scheduling , 2000, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000.

[28]  Yoji Kajitani,et al.  The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization , 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

[29]  Marco Platzner,et al.  Online scheduling and placement of real-time tasks to partially reconfigurable devices , 2003, RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003.