On SAT-Based Attacks On Encrypted Sequential Logic Circuits

Logic encryption has emerged as a solution to the hardware intellectual property (IP) protection prob-lem. In recent years, many attack methods have been proposed to counter the protection offered by logic encryption. Most state-of-the-art logic encryption schemes have been shown to be susceptible to one or more of these attack methods. Furthermore, defense methods on sequential circuits assume that a Boolean satisfiability (SAT) based attack can be applied to a sequential circuit only in the presence of a design-for-testability (DFT) architecture. In this paper, we examine the effectiveness of applying the SAT-based attack on logic encrypted sequential circuits lacking a scan architecture. We evaluate the effect of the presence of flip-flop chains in the circuit on the sequential SAT attack time. Furthermore, we analyze the evaluation results and propose an enhancement to the sequential SAT attack.

[1]  Giorgio Di Natale,et al.  A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[2]  Ankur Srivastava,et al.  Mitigating SAT Attack on Logic Locking , 2016, CHES.

[3]  Avesta Sasan,et al.  SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware , 2018, ACM Great Lakes Symposium on VLSI.

[4]  Jeyavijayan Rajendran,et al.  What to Lock?: Functional and Parametric Locking , 2017, ACM Great Lakes Symposium on VLSI.

[5]  Hai Zhou,et al.  CycSAT: SAT-based attack on cyclic logic encryptions , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[6]  Rohit Kapur,et al.  Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits , 2018, ArXiv.

[7]  Yung-Chih Chen.  Enhancements to SAT Attack , 2018, ACM Trans. Design Autom. Electr. Syst..

[8]  Meng Li,et al.  Cyclic Obfuscation for Creating SAT-Unresolvable Circuits , 2017, ACM Great Lakes Symposium on VLSI.

[10]  Jarrod A. Roy,et al.  EPIC: Ending Piracy of Integrated Circuits , 2008, 2008 Design, Automation and Test in Europe.

[11]  Ujjwal Guin,et al.  Counterfeit Integrated Circuits , 2015 .

[12]  John Villasenor,et al.  Chop shop electronics , 2013, IEEE Spectrum.

[13]  Meng Li,et al.  AppSAT: Approximately deobfuscating integrated circuits , 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[14]  Meng Li,et al.  Provably Secure Camouflaging Strategy for IC Protection , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Swarup Bhunia,et al.  HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Jeyavijayan Rajendran,et al.  CamoPerturb: Secure IC camouflaging for minterm protection , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  Domenic Forte,et al.  Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks , 2017, CHES.

[18]  David Z. Pan,et al.  Revisit sequential logic obfuscation: Attacks and defenses , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[19]  Hai Zhou,et al.  Double DIP: Re-Evaluating Security of Logic Encryption Algorithms , 2017, ACM Great Lakes Symposium on VLSI.

[20]  Ozgur Sinanoglu,et al.  SARLock: SAT attack resistant logic locking , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[21]  Siddharth Garg,et al.  Reverse engineering camouflaged sequential circuits without scan access , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[22]  Sayak Ray,et al.  Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[23]  Jeyavijayan Rajendran,et al.  Removal Attacks on Logic Locking and Camouflaging Techniques , 2020, IEEE Transactions on Emerging Topics in Computing.

[24]  Ioannis Savidis,et al.  Time Domain Sequential Locking for Increased Security , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).