Design and implementation of High Performance Visual Stimulator for Brain Computer Interfaces

An algorithm for implementing visual stimulators on generic computers has been developed for brain computer interfaces (BCIs). It uses the hardware counter present in these systems to derive accurate timing. Simultaneous display of 20 patterns (e.g. 3times3 checkerboards) modulated at different frequencies is possible. The pattern used for stimulating the steady state visual evoked potential (SSVEP) can be changed with ease. The stimulators are evaluated using software counters. High accuracy (less than 0.73% error) and precision (0.1% coefficient of variation) is recorded for 20 patterns set with frequencies between 6 Hz and 15 Hz

[1]  G Calhoun,et al.  Brain-computer interfaces based on the steady-state visual-evoked response. , 2000, IEEE transactions on rehabilitation engineering : a publication of the IEEE Engineering in Medicine and Biology Society.

[2]  Xiaorong Gao,et al.  Design and implementation of a brain-computer interface with high transfer rates , 2002, IEEE Transactions on Biomedical Engineering.

[3]  G. Pfurtscheller,et al.  Brain-Computer Interfaces for Communication and Control. , 2011, Communications of the ACM.

[4]  E Donchin,et al.  Brain-computer interface technology: a review of the first international meeting. , 2000, IEEE transactions on rehabilitation engineering : a publication of the IEEE Engineering in Medicine and Biology Society.

[5]  Xiaorong Gao,et al.  A BCI-based environmental controller for the motion-disabled. , 2003, IEEE transactions on neural systems and rehabilitation engineering : a publication of the IEEE Engineering in Medicine and Biology Society.

[6]  G.E. Birch,et al.  A general framework for brain-computer interface design , 2003, IEEE Transactions on Neural Systems and Rehabilitation Engineering.