CAD tools for ASIC design

Computer aids have been used for both the design and verification of electronic systems for many years. The recent explosion in the complexity of electronic systems that the advent of Very Large Scale Integration (VLSI) has allowed, has made the use of sophisticated computer-aided design tools indispensable. Computer aids will soon also provide key proprietary advantages as semiconductor and system design houses vie for the promising Application-Specific IC (ASIC) market of the next decade. This paper focusses on the techniques critical to both custom and ASIC design, the directions of present research and development for these areas, and future trends. In particular, recent developments in tools for the automated design of combinational logic are reviewed. These techniques include both algorithmic and rule-based approaches.

[1]  Roy A. Wood.  A High Density Programmable Logic Array Chip , 1979, IEEE Transactions on Computers.

[2]  William W. Cohen,et al.  A Rule-Based System for Optimizing Combinational Logic , 1985, IEEE Design & Test of Computers.

[3]  A. Weinberger.  Large Scale Integration of MOS Complex Logic: A Layout Method , 1967 .

[4]  Jean-Pierre Dussault,et al.  A High Level Synthesis Tool for MOS Chip Design , 1984, 21st Design Automation Conference Proceedings.

[5]  W. Fichtner,et al.  The VLSI Design Automation Assistant: From Algorithms to Silicon , 1985, IEEE Design & Test of Computers.

[6]  Dave Johannsen,et al.  Bristle Blocks: A Silicon Compiler , 1979, 16th Design Automation Conference.

[7]  Srinivas Devadas,et al.  GENIE: A Generalized Array Optimizer for VLSI Synthesis , 1986, 23rd ACM/IEEE Design Automation Conference.

[8]  Tsutomu Sasao,et al.  Input Variable Assignment and Output Phase Optimization of PLA's , 1984, IEEE Transactions on Computers.

[9]  Daniel Brand.  Redundancy and Don't Cares in Logic Synthesis , 1983, IEEE Transactions on Computers.

[10]  Juris Hartmanis,et al.  On the State Assignment Problem for Sequential Machines. I , 1961, IRE Trans. Electron. Comput..

[11]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Louise Trevillyan,et al.  LSS: A system for production logic synthesis , 1984, IBM Journal of Research and Development.

[13]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[14]  John Wyn Jones.  Array Logic Macros , 1975, IBM J. Res. Dev..

[15]  Tom Blank,et al.  A Survey of Hardware Accelerators Used in Computer-Aided Design , 1984, IEEE Design & Test of Computers.

[16]  A.R. Newton,et al.  Computer-aided design of VLSI circuits , 1981, Proceedings of the IEEE.

[17]  Daniel L. Ostapko,et al.  MINI: A Heuristic Approach for Logic Minimization , 1974, IBM J. Res. Dev..

[18]  A. R. Newton.  A Survey of Computer Aids for VLSI Layout , 1982, 1982 Symposium on VLSI Technology. Digest of Technical Papers.

[19]  J. Soukup.  Circuit layout , 1981, Proceedings of the IEEE.

[20]  Donald E. Thomas,et al.  Automatic Data Path Synthesis , 1983, Computer.

[21]  Srinivas Devadas,et al.  GENIE: A Generalized Array Optimizer for VLSI Synthesis , 1986, DAC 1986.