Schedulability analysis of global memory-predictable scheduling

The use of multicore CPUs in real-time systems poses significant challenges in estimating their temporal behavior. A factor that has a large impact on this issue is the contention for access to main memory among multiple cores. To overcome this problem, an execution model called PREM has been previously introduced to co-schedule CPU execution and accesses to main memory without relying on hardware arbiters. In this paper, we provide a global schedulbil-ity analysis for this predictable execution model, and we prove its correctness. We also evaluate the effectiveness of the proposed solution with extensive simulations. The results show a significant advantage of the proposed solution when compared to contention execution in which tasks access main memory unpredictably.

[1]  Giuseppe Lipari,et al.  Improved schedulability analysis of EDF on multiprocessor platforms , 2005, 17th Euromicro Conference on Real-Time Systems (ECRTS'05).

[2]  Wang Yi,et al.  Schedulability analysis for non-preemptive fixed-priority multiprocessor scheduling , 2011, J. Syst. Archit..

[3]  Lui Sha,et al.  MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms , 2013, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).

[4]  Rodolfo Pellizzoni,et al.  Time-predictable execution of multithreaded applications on multicore systems , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  James H. Anderson,et al.  On the Scalability of Real-Time Scheduling Algorithms on Multicore Platforms: A Case Study , 2008, 2008 Real-Time Systems Symposium.

[6]  Marco Caccamo,et al.  Memory-centric scheduling for multicore hard real-time systems , 2012, Real-Time Systems.

[7]  Wang Yi,et al.  New Schedulability Test Conditions for Non-preemptive Scheduling on Multiprocessor Platforms , 2008, 2008 Real-Time Systems Symposium.

[8]  Lars Lundberg,et al.  Multiprocessor scheduling of age constraint processes , 1998, Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236).

[9]  Lothar Thiele,et al.  Worst case delay analysis for memory interference in multicore systems , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[10]  Xue Liu,et al.  Integrating Adaptive Components: An Emerging Challenge in Performance-Adaptive Systems and a Server Farm Case-Study , 2007, 28th IEEE International Real-Time Systems Symposium (RTSS 2007).

[11]  Hugues Cassé,et al.  Deterministic Execution Model on COTS Hardware , 2012, ARCS.

[12]  Hennadiy Leontyev,et al.  A Unified Hard/Soft Real-Time Schedulability Test for Global EDF Multiprocessor Scheduling , 2008, 2008 Real-Time Systems Symposium.

[13]  Alan Burns,et al.  Global fixed priority scheduling with deferred pre-emption , 2013, 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications.

[14]  O. Mutlu,et al.  Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems , 2010, ASPLOS XV.

[15]  Theodore P. Baker,et al.  Multiprocessor EDF and deadline monotonic schedulability analysis , 2003, RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003.

[16]  Björn B. Brandenburg,et al.  Cache-Related Preemption and Migration Delays : Empirical Approximation and Impact on Schedulability ∗ , 2010 .

[17]  Alan Burns,et al.  A survey of hard real-time scheduling for multiprocessor systems , 2011, CSUR.

[18]  Sanjoy K. Baruah,et al.  The Non-preemptive Scheduling of Periodic Tasks upon Multiprocessors , 2006, Real-Time Systems.

[19]  Petru Eles,et al.  Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip , 2007, RTSS.

[20]  Michael Paulitsch,et al.  Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[21]  James E. Smith,et al.  Fair Queuing Memory Systems , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[22]  Jan Reineke,et al.  Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  L. Thiele,et al.  Timing Predictability on Multi-Processor Systems with Shared Resources , 2009 .

[24]  Sanjoy K. Baruah.  Techniques for Multiprocessor Global Schedulability Analysis , 2007, 28th IEEE International Real-Time Systems Symposium (RTSS 2007).

[25]  Alan Burns,et al.  Improved priority assignment for global fixed priority pre-emptive scheduling in multiprocessor real-time systems , 2010, Real-Time Systems.

[26]  Alexandra Fedorova,et al.  Addressing shared resource contention in multicore processors via scheduling , 2010, ASPLOS XV.

[27]  Marco Caccamo,et al.  A Predictable Execution Model for COTS-Based Embedded Systems , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.