Application specific multi-port memory customization in FPGAs
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[1] Michael D. Smith,et al. Boosting beyond static scheduling in a superscalar processor , 1990, ISCA '90.
[2] Gorker Alp Malazgirt,et al. MIPT: Rapid exploration and evaluation for migrating sequential algorithms to multiprocessing systems with multi-port memories , 2014, 2014 International Conference on High Performance Computing & Simulation (HPCS).
[3] Harish Patil,et al. Pin: building customized program analysis tools with dynamic instrumentation , 2005, PLDI '05.
[4] Joseph A. Fisher,et al. Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.
[5] J. Gregory Steffan,et al. Efficient multi-ported memories for FPGAs , 2010, FPGA '10.
[6] Rawan Naous,et al. A Configurable Multi-ported Register File Architecture for Soft Processor Cores , 2007, ARC.
[7] Arda Yurdakul,et al. Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs , 2013, 2013 Euromicro Conference on Digital System Design.
[8] Peter Y.-T. Hsu,et al. Highly concurrent scalar processing , 1986, ISCA '86.
[9] Thierry Lecroq,et al. The exact online string matching problem: A review of the most recent results , 2013, CSUR.
[10] Monica S. Lam,et al. Efficient context-sensitive pointer analysis for C programs , 1995, PLDI '95.
[11] Stephan Wong,et al. A multiported register file with register renaming for configurable softcore VLIW processors , 2010, 2010 International Conference on Field-Programmable Technology.