Design of Fastest Multiplier Using Area–Delay– Power Efficient Carry-Select Adder

Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the area, time and power efficient carry select adder. In previous we read about the designing of multipliers using the ripple carry adders. By using the ripple carry adders the propagation delay is high. To overcome this problem we are using the carry select adder in this paper. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed multiplier design involves significantly less area and delay than the recently proposed multipliers.