Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC

In complex embedded applications, optimization and adaptation at run time of both dynamic and leakage power have become an issue at SoC coarse grain. For power reduction, voltage and frequency scaling techniques have been applied successfully to CPUs but never with a generic approach for all IPs within a SoC. Network-on-Chip architecture combined with a globally asynchronous locally synchronous paradigm is a natural enabler for easy IP unit integration. GALS NoC provides scalable communications and a clear split between timing domains. We propose in this paper a complete dynamic voltage and frequency scaling architecture for IP units integration within a GALS NOC. The proposed DVFS architecture is based on the association of local clock generator and VDD-hopping between two given voltages. No fine control software is required during any voltage and frequency re-programming. As a result, minimal latency cost is observed. The power efficiency of the proposed system has been evaluated close to 95%.

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