FPGA Implementing of Turbo Encoder

Use FPGA to realize the Turbo coder of CDMA2000 system. Its interlace instrument consists of a synchronization dual-port RAM and a ROM. The RAM stores the input coding data and the ROM is the search list of interlace address. When inputting data, the input data effectively displays the data input and carries out input synchronization. At the same time, write data to RAM, the ROM stops. After writing, a data frame reads a data from ROM as interlace address, and acquires useful data for coding. The time control module provides RAM with written address. The ROM output provides address for reading RAM. The read write control is managed by the control module.