A simulation-based temporal assertion checker for PSL

A simulation-based temporal assertion verification engine for PSL (property specification language), called Tempral Wizard, is proposed in this paper. It is very efficient because its time and space complexity are both O(n). A new concept, tag, is introduced in Tempral Wizard and it handles the forall operator elegantly.

[1]  William P. Birmingham,et al.  A symbolic-simulation approach to the timing verification of interacting FSMs , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[2]  Koji Ara,et al.  A proposal for transaction-level verification with Component Wrapper Language , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[3]  Thomas W. Williams,et al.  An industrial view of electronic design automation , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..