Applying the zeros switch-off technique to reduce static energy in data caches
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[1] James E. Smith,et al. Very low power pipelines using significance compression , 2000, MICRO 33.
[2] David Blaauw,et al. Drowsy caches: simple techniques for reducing leakage power , 2002, ISCA.
[3] Andreas Moshovos,et al. Low-leakage asymmetric-cell SRAM , 2002, ISLPED '02.
[4] Dr. Danny Rittman. Power Optimization Within Nanometer Designs , 2005 .
[5] Mateo Valero,et al. A content aware integer register file organization , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[6] Krste Asanovic,et al. Dynamic zero compression for cache energy reduction , 2000, MICRO 33.
[7] Margaret Martonosi,et al. Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.
[8] Feipei Lai,et al. Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories , 2005, IEEE Micro.
[9] Jun Yang,et al. Energy efficient Frequent Value data Cache design , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..
[10] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[11] Jun Yang,et al. Frequent value locality and value-centric data cache design , 2000, SIGP.
[12] Kaushik Roy,et al. Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.