Setting and validating precision requirements in the digital VLSI implementation of a neural defect-identifier for machined objects

In this paper we deal with the functional design of a dedicated digital VLSI neurochip for a real time demanding application: the identification of defects in machined parts of mechanical objects. Precision requirements analysis (in terms of the bits number to represent neural values) represents a critical point to be faced when choosing the final architecture since requirements on the chip's size may prevent parallelism exploitation. Application features and neural dynamics are thus carefully analysed to determine quasi-minimal bit requirements for the architectural components. Afterwards, once the hardware design has been defined, sensitivity analysis tools need to be applied to validate effective performances. It is shown that an accurate choice of precision requirements for hardware elements, despite poor signal to noise ratios, leads to a suitable architecture which solves the application and makes feasible the VLSI design.<<ETX>>