On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs
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Alessandro Barenghi | Christof Paar | Amir Moradi | Timo Kasper | C. Paar | Alessandro Barenghi | A. Moradi | Timo Kasper
[1] P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .
[2] Alfred Menezes,et al. Handbook of Applied Cryptography , 2018 .
[3] Rodham E. Tulloss,et al. The Test Access Port and Boundary Scan Architecture , 1990 .
[4] Tim Güneysu,et al. Cryptanalysis with COPACOBANA , 2008, IEEE Transactions on Computers.
[5] Giovanni Agosta,et al. Record Setting Software Implementation of DES Using CUDA , 2010, 2010 Seventh International Conference on Information Technology: New Generations.
[6] Bart Preneel,et al. Power-Analysis Attacks on an FPGA - First Experimental Results , 2003, CHES.
[7] Christophe Clavier,et al. Correlation Power Analysis with a Leakage Model , 2004, CHES.
[8] Siva Sai Yerubandi,et al. Differential Power Analysis , 2002 .
[9] Tim Güneysu,et al. Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering , 2009, CHES.
[10] Bart Preneel,et al. Power Analysis Attacks Against FPGA Implementations of the DES , 2004, FPL.
[11] Eric Peeters,et al. Power and electromagnetic analysis: Improved model, consequences and comparisons , 2007, Integr..
[12] Jean-Baptiste Note,et al. From the bitstream to the netlist , 2008, FPGA '08.
[13] Dennis G. Abraham,et al. Transaction Security System , 1991, IBM Syst. J..
[14] Ralf Krueger. Using High Security Features in Virtex-II Series FPGAs , 2004 .
[15] Ieee Standard Test Access Port and Boundary-scan Architecture Ieee-sa Standards Board , 2001 .
[16] Alessandro Barenghi,et al. Improving first order differential power attacks through digital signal processing , 2010, SIN.
[17] Christof Paar,et al. On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoqCode Hopping Scheme , 2008, CRYPTO.
[18] Christof Paar,et al. Security on FPGAs: State-of-the-art implementations and attacks , 2004, TECS.
[19] Alessandro Barenghi,et al. Information Leakage Discovery Techniques to Enhance Secure Chip Design , 2011, WISTP.
[20] Saar Drimer,et al. Security for volatile FPGAs , 2009 .