Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing
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Tadashi Shibata | Tadahiro Ohmi | Tatsuo Morimoto | Tsutomu Nakai | Takeo Yamashita | Ryu Kaihara | T. Shibata | T. Nakai | T. Morimoto | R. Kaihara | T. Yamashita | T. Ohmi
[1] Teuvo Kohonen,et al. Self-Organization and Associative Memory , 1988 .
[2] Teuvo Kohonen,et al. Self-Organization and Associative Memory, Second Edition , 1988, Springer Series in Information Sciences.
[3] John Lazzaro,et al. Winner-Take-All Networks of O(N) Complexity , 1988, NIPS.
[4] Tadashi Shibata,et al. A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .
[5] Tadashi Shibata,et al. Neuron MOS winner-take-all circuit and its application to associative memory , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[6] Tadashi Shibata,et al. Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors , 1993, NIPS.
[7] Tadahiro Ohmi,et al. Neuron MOS binary-logic integrated circuits. II. Simplifying techniques of circuit configuration and their practical applications , 1993 .
[8] Bing J. Sheu,et al. A high-precision VLSI winner-take-all circuit for self-organizing neural networks , 1993 .
[9] Masayuki Kawamata,et al. Evolutionary Digital Filters - adaptive digital filters based on evolutionary strategies of organisms - , 1994 .
[10] G. Cauwenberghs,et al. A Charge-Based CMOS Parallel Analog Vector Quantizer , 1994, NIPS 1994.
[11] Tadashi Shibata,et al. Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.