Leakage energy reduction in cache memory by data compression

Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory. Almost all of today's commercial processors, not only high-performance microprocessors but embedded ones, have on-chip cache memories. However, energy consumption in the cache memory would approach or exceed 50% of the total consumption by the processors, which leads to a serious problem in terms of allowable temperature and performance improvement. An important point to note is that, in the near future, static (leakage) energy will dominate the energy consumption in deep sub-micron processes. In this paper, we propose cache memory architecture that exploits gated-Vdd control per cache block and a dynamic data compression scheme in the secondary cache, and achieves efficient reduction of static energy consumed by the secondary cache memory. In the simulation using SPEC95 integer benchmarks, our technique reduced about 45% of leakage energy in the cache at maximum, and about 28% on average.

[1]  Jun Yang,et al.  Frequent value compression in data caches , 2000, MICRO 33.

[2]  Kaushik Roy,et al.  Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.

[3]  Koji Nii,et al.  A low power SRAM using auto-backgate-controlled MT-CMOS , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[4]  David A. Wood,et al.  Adaptive cache compression for high-performance processors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[5]  Bill Moyer,et al.  A low power unified cache architecture providing power and performance flexibility , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[6]  Kevin Skadron,et al.  State-preserving vs. non-state-preserving leakage control in caches , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  Jun Yang,et al.  Frequent Value Locality and Value-Centric Data Cache Design , 2000, ASPLOS.

[8]  Yan Meng,et al.  On the limits of leakage power reduction in caches , 2005, 11th International Symposium on High-Performance Computer Architecture.

[9]  Kaushik Roy,et al.  An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[10]  Margaret Martonosi,et al.  Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.

[11]  Trevor Pering,et al.  Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System , 1998 .

[12]  David Blaauw,et al.  Drowsy caches: simple techniques for reducing leakage power , 2002, ISCA.

[13]  David A. Wood,et al.  Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches , 2004 .

[14]  Pierfrancesco Foglia,et al.  ACM SIGARCH Computer Architecture News - Special Issue: Medea 2006 Workshop , 2007 .

[15]  Krste Asanovic,et al.  Dynamic fine-grain leakage reduction using leakage-biased bitlines , 2002, ISCA.

[16]  K. Tanaka,et al.  Static Energy Reduction in Cache Memories Using Data Compression , 2006, TENCON 2006 - 2006 IEEE Region 10 Conference.

[17]  C. R. Henson.  Conclusion , 1969 .

[18]  David L Weaver,et al.  The SPARC architecture manual : version 9 , 1994 .

[19]  S. Jones,et al.  Design and performance of a main memory hardware data compressor , 1996, Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies.