Conflicting needs complicate the task of testing LSI chips. As system designs come to require better and more predictable performance, it becomes increasingly difficult to develop tests for application at the product I/O pins to verify that each internal device has been manufactured correctly.
Any of numerous kinds of random manufacturing defect, though allowing correct dc operation, can cause a device to perform at a speed below that specified for it. This type of defect has led to the development of several testing methods that have become conventional. For numerous reasons, however, the conventional methods cannot be extended to LSI without certain design constraints.
For the LSSD—level-sensitive scan design—constraints, dc fault-oriented testing has been extended to delay faults. The strategy is to delay-test each block input and/or output in both its longest and its shortest sensitizable delay paths. An algorithm for automatic generation of such delay tests has been developed, and extended to generate delay tests for designer-specified critical paths.
[1]
Peter S. Bottorff,et al.
Automatic checking of logic design structures For compliance with testability ground rules
,
1977,
DAC '77.
[2]
Thomas W. Williams,et al.
A logic design structure for LSI testability
,
1977,
DAC '77.
[3]
Peter S. Bottorff,et al.
Test generation for large logic networks
,
1977,
DAC '77.
[4]
M. Correia,et al.
Introduction to an LSI test system
,
1977,
DAC '77.
[5]
Melvin A. Breuer.
The Effects of Races, Delays, and Delay Faults on Test Generation
,
1974,
IEEE Transactions on Computers.
[6]
Thomas M. Storey,et al.
Delay test simulation
,
1977,
DAC '77.