FPGA computing in a data parallel C
暂无分享,去创建一个
The authors demonstrate a new technique for automatically synthesizing digital logic from a high level algorithmic description in a data parallel language. The methodology has been implemented using the Splash 2 reconfigurable logic arrays for programs written in Data-parallel Bit-serial C (dbC). The translator generates a VHDL description of a SIMD processor array with one or more processors per Xilinx 4010 FPGA. The instruction set of each processor is customized to the dbC program being processed. In addition to the usual arithmetic operations, nearest neighbor communication, host-to-processor communication, and global reductions are supported.<<ETX>>
[1] Daniel P. Lopresti,et al. Building and using a highly parallel programmable logic array , 1991, Computer.