Quantum circuits for floating-point arithmetic

Quantum algorithms to solve practical problems in quantum chemistry, materials science, and matrix inversion often involve a significant amount of arithmetic operations which act on a superposition of inputs. These have to be compiled to a set of fault-tolerant low-level operations and throughout this translation process, the compiler aims to come close to the Pareto-optimal front between the number of required qubits and the depth of the resulting circuit. In this paper, we provide quantum circuits for floating-point addition and multiplication which we find using two vastly different approaches. The first approach is to automatically generate circuits from classical Verilog implementations using synthesis tools and the second is to generate and optimize these circuits by hand. We compare our two approaches and provide evidence that floating-point arithmetic is a viable candidate for use in quantum computing, at least for typical scientific applications, where addition operations usually do not dominate the computation. All our circuits were constructed and tested using the software tools LIQ\(Ui|\rangle {}\) and RevKit.

[1]  Giovanni De Micheli,et al.  Hierarchical reversible logic synthesis using LUTs , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[2]  Krysta Marie Svore,et al.  LIQUi|>: A Software Design Architecture and Domain-Specific Language for Quantum Computing , 2014, ArXiv.

[3]  Jason Cong,et al.  DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs , 2004, ICCAD 2004.

[4]  A. Harrow,et al.  Quantum algorithm for linear systems of equations. , 2008, Physical review letters.

[5]  Peter W. Shor,et al.  Algorithms for quantum computation: discrete logarithms and factoring , 1994, Proceedings 35th Annual Symposium on Foundations of Computer Science.

[6]  Rodney Van Meter,et al.  A Resource-Efficient Design for a Reversible Floating Point Adder in Quantum Computing , 2014, JETC.

[7]  Donald E. Knuth,et al.  Evaluation of polynomials by computer , 1962, Commun. ACM.

[8]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  A. Steane Overhead and noise threshold of fault-tolerant quantum error correction , 2002, quant-ph/0207119.

[10]  Mathias Soeken,et al.  Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Martin Rötteler,et al.  Factoring using $2n+2$ qubits with Toffoli based modular multiplication , 2016, Quantum Inf. Comput..

[12]  Giovanni De Micheli,et al.  Design automation and design space exploration for quantum computers , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[13]  Robert K. Brayton,et al.  Mapping into LUT structures , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  Cody Jones,et al.  Low-overhead constructions for the fault-tolerant Toffoli gate , 2012, 1212.5069.

[15]  Rolf Drechsler,et al.  Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition , 2015, RC.

[16]  I. Chuang,et al.  Quantum Computation and Quantum Information: Bibliography , 2010 .

[17]  Annie Y. Wei,et al.  Exponentially more precise quantum simulation of fermions in second quantization , 2015, 1506.01020.

[18]  Yasuhiro Takahashi,et al.  Quantum addition circuits and unbounded fan-out , 2009, Quantum Inf. Comput..

[19]  M. Troyer,et al.  Elucidating reaction mechanisms on quantum computers , 2016, Proceedings of the National Academy of Sciences.