A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery
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[1] Hashida Takushi,et al. 32 Gb/s Data-Interpolator Receiver with 2-tap DFE in 28-nm CMOS , 2013 .
[2] Un-Ku Moon,et al. A Wide-Tracking Range Clock and Data Recovery Circuit , 2008, IEEE Journal of Solid-State Circuits.
[3] Wei-Zen Chen,et al. A 3.12 pJ/bit, 19–27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery , 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).
[4] A. Rylyakov. An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 6Snm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.
[5] Thomas Toifl,et al. A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology , 2012, IEEE Journal of Solid-State Circuits.
[6] Takayuki Shibasaki,et al. 22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.
[7] T.O. Dickson,et al. A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology , 2008, IEEE Journal of Solid-State Circuits.
[8] Alexander V. Rylyakov,et al. A 28 GHz Hybrid PLL in 32 nm SOI CMOS , 2014, IEEE Journal of Solid-State Circuits.
[9] Paul J. Hurst,et al. A mixed-signal decision-feedback equalizer that uses a look-ahead architecture , 1997 .
[10] E. Alon,et al. Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery , 2005, IEEE Journal of Solid-State Circuits.
[11] Amir Amirkhany,et al. A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[12] Paul J. Hurst,et al. An analog DFE for disk drives using a mixed-signal integrator , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
[13] Thomas H. Lee,et al. A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[14] Behzad Razavi,et al. A 25 Gb/s 5.8 mW CMOS Equalizer , 2015, IEEE Journal of Solid-State Circuits.
[15] Hong-June Park,et al. A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[16] Masum Hossain,et al. A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.
[17] P. Larsson,et al. A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability , 1999, IEEE J. Solid State Circuits.
[18] W. Walker,et al. A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[19] Shreyas Sen,et al. A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.
[20] Yong Liu,et al. A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS , 2012, IEEE Journal of Solid-State Circuits.
[21] Michael Frueh,et al. Design Of Integrated Circuits For Optical Communications , 2016 .
[22] Mark Horowitz,et al. A 700-Mb/s/pin CMOS signaling interface using current integrating receivers , 1997 .
[23] Behzad Razavi,et al. A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.
[24] A. Rylyakov,et al. A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions , 2007, IEEE Journal of Solid-State Circuits.
[25] Yung Sern Tan,et al. A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[26] Chih-Kong Ken Yang,et al. Edge and Data Adaptive Equalization of Serial-Link Transceivers , 2008, IEEE Journal of Solid-State Circuits.