A neural network approach to topological via-minimization problems

Topological via-minimization (TVM) algorithms in two-layer channels based on the artificial neural network model are presented. TVM problems require not only assigning wires or nets between terminals to one of two layers without an intersection, but also minimizing the number of vias, which are the single contacts between the nets in the two layers. The goal of the algorithm is to embed the maximum number of nets without an intersection. Two types of TVM problems are examined: split rectangular TVM (RTVM) problems and split circular TVM (CTVM) problems. The algorithms require 3n processing elements for the n-net split RTVM problems, and 5n processing elements for the n-net split CTVM problems. The algorithms were verified by solving seven problems with 20 to 80 nets. The algorithms can be easily extended to problems with more than two layers. >

[1]  David Hung-Chang Du,et al.  Layer Assignment Problem for Three-Layer Routing , 1988, IEEE Trans. Computers.

[2]  Yoshiyasu Takefuji,et al.  A parallel improvement algorithm for the bipartite subgraph problem , 1992, IEEE Trans. Neural Networks.

[3]  Yoshiyasu Takefuji,et al.  A Parallel Algorithms for Traffic Control Problems in Three-Stage Connecting Networks , 1994, J. Parallel Distributed Comput..

[4]  Majid Sarrafzadeh,et al.  A new approach to topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Malgorzata Marek-Sadowska.  An Unconstrained Topological Via Minimization Problem for Two-Layer Routing , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Yoshiyasu Takefuji,et al.  Artificial neural networks for four-coloring map problems and K-colorability problems , 1991 .

[7]  Maciej J. Ciesielski,et al.  An Optimum Layer Assignment for Routing in ICs and PCBs , 1981, 18th Design Automation Conference.

[8]  Alberto Sangiovanni-Vincentelli,et al.  Mighty: a rip-up and reroute detailed router , 1986 .

[9]  Toshinobu Kashiwabara,et al.  Exact algorithms for multilayer topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  T. C. Chern,et al.  Fast algorithm for optimal layer assignment , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[11]  Yoji Kajitani,et al.  A graph- theoretic via minimization algorithm for two layer printed circuit boards , 1983 .

[12]  Ernest S. Kuh,et al.  A unified approach to the via minimization problem , 1989 .

[13]  Sumio Masuda,et al.  The Via Minimization Problem is NP-Complete , 1989, IEEE Trans. Computers.

[14]  Yoshiyasu Takefuji,et al.  A Neural Network Model for Finding a Near-Maximum Clique , 1992, J. Parallel Distributed Comput..

[15]  Ernest S. Kuh,et al.  The constrained via minimization problem for PCB and VLSI design , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[16]  Xiong Xiao-Ming.  A new algorithm for topological routing and via minimization , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[17]  Yoshiyasu Takefuji,et al.  A parallel algorithm for channel routing problems [VLSI] , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  KENNETH J. SUPOWIT,et al.  Finding a Maximum Planar Subset of a Set of Nets in a Channel , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Hyeong-Ah Choi,et al.  Graph Bipartization and via Minimization , 1989, SIAM J. Discret. Math..

[20]  Y Takefuji,et al.  A Near-Optimum Parallel Planarization Algorithm , 1989, Science.

[21]  Yoshiyasu Takefuji,et al.  Comparisons of Seven Neural Network Models on Traffic Control Problems in Multistage Interconnection Networks , 1993, IEEE Trans. Computers.

[22]  David Hung-Chang Du,et al.  Efficient Algorithms for Layer Assignment Problem , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  W. Pitts,et al.  A Logical Calculus of the Ideas Immanent in Nervous Activity (1943) , 2021, Ideas That Created the Future.

[24]  Yoshiyasu Takefuji,et al.  A parallel algorithm for allocation of spare cells on memory chips , 1991 .

[25]  Chi-Ping Hsu.  Minimum-Via Topological Routing , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Yoshiyasu Takefuji,et al.  A neural network parallel algorithm for clique vertex-partition problems , 1992 .

[27]  Yoshiyasu Takefuji,et al.  A parallel algorithm for tiling problems , 1990, IEEE Trans. Neural Networks.

[28]  Akihiro Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC.