Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are sought on the grounds that: (1) Si seems to have reached its technological and performance limits and (2) the use of alternative high-mobility channel materials will provide the missing performance. With the help of numerical simulations here we establish the reasons why indeed Si seems to have hit an intrinsic performance barrier and whether or not high mobility semiconductors can indeed grant us our wishes. The role of long-and short-range electron-electron interactions are revisited together with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues are also reviewed to see what advantage alternative substrates may bring us. Finally, the well-known ‘virtual source model’ is analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length.

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