Infrastructure IP for configuration and test of boards and systems
暂无分享,去创建一个
Embedding infrastructure IP to optimize chip-level manufacturing test and debugging has recently become common practice. However, adopting the same approach for boards and systems requires a different family of infrastructure IP. This article introduces such a family and discusses how it can optimize manufacturing test and debugging, as well as support configurability, especially in today's reconfigurable products.
[1] Yervant Zorian. Guest Editor's Introduction: What is Infrastructure IP? , 2002, IEEE Des. Test Comput..
[2] Kenneth P. Parker,et al. Boundary scan signals future age of test , 2002 .
[3] Peter Collins,et al. Hierarchical boundary-scan: a Scan Chip-Set solution , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[4] Rodham E. Tulloss,et al. The Test Access Port and Boundary Scan Architecture , 1990 .