VLSI Implementation of Restricted Coulomb Energy Neural Network with Improved Learning Scheme

This paper proposes a restricted coulomb energy neural network (RCE-NN) with an improved learning algorithm and presents the hardware architecture design and VLSI implementation results. The learning algorithm of the existing RCE-NN applies an inefficient radius adjustment, such as learning all neurons at the same radius or reducing the radius excessively in the learning process. Moreover, since the reliability of eliminating unnecessary neurons is estimated without considering the activation region of each neuron, it is inaccurate and leaves unnecessary neurons extant. To overcome this problem, the proposed learning algorithm divides each neuron region in the learning process and measures the reliability with different factors for each region. In addition, it applies a process of gradual radius reduction by a pre-defined reduction rate. In performance evaluations using two datasets, RCE-NN with the proposed learning algorithm showed high recognition accuracy with fewer neurons compared to existing RCE-NNs. The proposed RCE-NN processor was implemented with 197.8K logic gates in 0.535 mm 2 using a 55 nm CMOS process and operated at the clock frequency of 150 MHz.

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