A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm With 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant-<inline-formula> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/°C, and a variability <inline-formula> <tex-math notation="LaTeX">$(\sigma /\mu)$ </tex-math></inline-formula> of 1.66 %. Then, two 4T+1R <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula>-range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09-<inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> (resp. 0.99-<inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula>) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/°C (resp. 290-ppm/°C) TC, and a 0.87-% (resp. 0.65-%) <inline-formula> <tex-math notation="LaTeX">$(\sigma /\mu)$ </tex-math></inline-formula>. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations.

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