High-Voltage Thin-SOI LDMOS With Ultralow ON-Resistance and Even Temperature Characteristic

An ultralow specific ON-resistance (RON,sp) thin-silicon-on-insulator (SOI) LDMOS is proposed. Its ON-state and OFF-state mechanisms and thermal characteristic are investigated by simulation. It features an accumulation extended gate (AEG) structure on the surface and the AEG consists of a p-region and two integrated diodes. In the ON-state, the high density electron accumulation layer formed in the drift region surface provides an extremely low-resistance current path, which dramatically decreases the RON,sp and eases the dependence of RON,sp on the drift doping concentration (Nd) . Meanwhile, the charge compensation effect between the drift region and the p-region of AEG allows a higher Nd value and then further decreases RON,sp. Consequently, the AEG contributes to an ultralow RON,sp owing to the accumulation layer and the charge compensation effect. On the other hand, the thin SOI of the proposed device adopts variable lateral doping (VLD) to realize high breakdown voltage (BV). Note that the intrinsic hotspot effect caused by the thin VLD SOI is overcome and, thus, the proposed device obtains a lower and evenly distributed surface temperature in the ON-state, owing to the accumulation layer along the drift region surface. Moreover, the two reverse biased diodes in the AEG sustain the gate-drain voltage in the ON-state and OFF-state, respectively, ensuring low current leakage and high BV. Therefore, compared with the VLD SOI LDMOS at the same dimensions, the proposed device not only decreases RON,sp by 65% and increases the BV by 7%, but also obtains an even surface temperature distribution and decreases the maximum surface temperature by 52 K at the same power density.

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