FPGA implementation of image dehazing algorithm for real time applications

Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

[1]  Shree K. Nayar,et al.  Contrast Restoration of Weather Degraded Images , 2003, IEEE Trans. Pattern Anal. Mach. Intell..

[2]  Shih-Chia Huang,et al.  Visibility Restoration of Single Hazy Images Captured in Real-World Weather Conditions , 2014, IEEE Transactions on Circuits and Systems for Video Technology.

[3]  Raanan Fattal,et al.  Single image dehazing , 2008, ACM Trans. Graph..

[4]  Robby T. Tan,et al.  Visibility in bad weather from a single image , 2008, 2008 IEEE Conference on Computer Vision and Pattern Recognition.

[5]  Weisheng Li,et al.  Single image haze removal based on haze physical characteristics and adaptive sky region detection , 2016, Neurocomputing.

[6]  Holger Blume,et al.  HLS-based FPGA implementation of a predictive block-based motion estimation algorithm — A field report , 2014, Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing.

[7]  Hans-Peter Seidel,et al.  3D-modeling by ortho-image generation from image sequences , 2008, ACM Trans. Graph..

[8]  Ranga Rodrigo,et al.  HLS approach in designing FPGA-based custom coprocessor for image preprocessing , 2010, 2010 Fifth International Conference on Information and Automation for Sustainability.

[9]  Yu Ting Chen,et al.  A Survey and Evaluation of FPGA High-Level Synthesis Tools , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Xiaoou Tang,et al.  Single Image Haze Removal Using Dark Channel Prior , 2011 .

[11]  Yong Dou,et al.  A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications , 2007, 2007 Asia and South Pacific Design Automation Conference.

[12]  Stephen Neuendorffer,et al.  Accelerating OpenCV Applications with Zynq-7000 All Programmable SoC using Vivado HLS Video Libraries , 2013 .

[13]  Pei-Yin Chen,et al.  Hardware Implementation of a Fast and Efficient Haze Removal Method , 2013, IEEE Transactions on Circuits and Systems for Video Technology.