VLSI architecture of forward and inverse quantization modules of H.264 for HD transmission

The latest video compression standard H.264 has introduced novel algorithms for quantization and inverse quantization processes. In this paper, new hardware architectures are proposed for the forward quantizer and inverse quantizer blocks for real-time video processing. Implemented in Xilinx 14.1, Virtex-5 technology, the designed architectures for quantizer and its inverse have a critical path delay of 11.62 ns and 10.87 ns respectively. The proposed designs when integrated with other modules of transform domain of H.264 can achieve the speed requirement of HD-1080 video format at 30 frames per second.