Ultra-high-density 3D chip stacking technology

The 3D chip stacked LSI technology under development in ASET is a new packaging technology to realize highdensity and high-speed transmission. Two key technologies is necessary to realize the 3D chip stacked LSI. One is low temperature simple interconnection of Cn through electrodes in 20 pm pitch. Other is encapsulation of super narrow gap less than 10 pm between devices. The Cu bump bonding (CBB) process utilizing Sn capped Cu Bump was evaluated, and connection at 245°C and 150T by formation of the inter metallic compound (IMC) as qCu&n5 was confumed. The post aging process was applied to form the complete diffusion layer between Cn bumps after bonding, and the IMC layer was only consist of E-Cu,Sn, and considered to be stable against the thermal stress after chip stacking process. In addition, the non-conductive particle paste (NCP) preform process was evaluated. The micro thin gap was almost encapsulated without void. ,Moreover the chip backside warpage after bonding was very small less than 3 pm, and considered to realize stacking chip onto the stable bonding area. Finally, The mechanical sample of 3D chip stacked module with Cu through electrodes in 20 pm pitch was build snccessfidly utilizing CBB and NCP preform process.

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