Optimal BIST using an embedded microprocessor

Systems-on-a-chip (SOCs) with many complex intellectual property (IP) cores require a large number of test patterns and a large volume of data. The computing power of the embedded processor in an SOC can be used to test the cores within the chip boundary, reducing the test time and memory requirements. This paper discusses techniques that use the computing power of the embedded processor in a more sophisticated way to significantly reduce memory requirements and the number of test applications, and hence the testing time. The processor can generate random patterns and selectively apply those patterns that contribute to the fault coverage. It can also apply deterministic test patterns that have been compressed using the characteristics of the random patterns as well as the deterministic patterns themselves. Fast run-length coding schemes which are easily implemented and effective for test data compression are described.

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