A Fast JPEG2000 Encoder That Preserves Coding Efficiency: The Split Arithmetic Encoder

Embedded block coding, i.e., embedded block coder with optimal truncation (EBCOT) tier-1, is the most computationally intensive part of the JPEG2000 image coding standard. Past research on fast EBCOT tier-1 hardware implementations has concentrated on cycle-efficient context formation. These pass-parallel architectures require that JPEG2000's three mode switches be turned on; thus, coding efficiency is sacrificed for improved throughput. In this paper, a new fast EBCOT tier-1 design is presented: It is called the split arithmetic encoder (SAE) process. The proposed process exploits concurrency to obtain improved throughput while preserving coding efficiency. The SAE process is evaluated using the following three methods: clock cycle estimation, multithreaded software implementation, and FPGA hardware implementation. All three methods achieve throughput improvement; the hardware implementation exhibits the largest speedup, as expected. The benefits of evaluating a proposed process (algorithm) from different perspectives are illustrated.

[1]  Dirk Grunwald,et al.  Methods for modeling resource contention on simultaneous multithreading processors , 2005, 2005 International Conference on Computer Design.

[2]  Wu Tuo,et al.  A cycle-efficient sample-parallel EBCOT architecture for JPEG2000 encoder , 2004, Proceedings of 2004 International Symposium on Intelligent Multimedia, Video and Speech Processing, 2004..

[3]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[4]  Dinesh Bhatia,et al.  FPGA based EBCOT architecture for JPEG 2000 , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

[5]  Chih-Hsien Hsia,et al.  High-speed EBCOT with dual context-modeling coding architecture for JPEG2000 , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[6]  Touradj Ebrahimi,et al.  The JPEG 2000 still image compression standard , 2001, IEEE Signal Process. Mag..

[7]  Magdy A. Bayoumi,et al.  A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000 , 2006, IEEE Transactions on Circuits and Systems for Video Technology.

[8]  David S. Taubman,et al.  Concurrency techniques for arithmetic coding in JPEG2000 , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Yizhen Zhang,et al.  Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000 , 2007, IEEE Transactions on Circuits and Systems for Video Technology.

[10]  Jen-Shiun Chiang,et al.  Efficient pass-parallel architecture for EBCOT in JPEG2000 , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[11]  Liang-Gee Chen,et al.  Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000 , 2003, IEEE Trans. Circuits Syst. Video Technol..

[12]  Yu-Wei Chang,et al.  High performance two-symbol arithmetic encoder in JPEG 2000 , 2004, IEEE International Symposium on Consumer Electronics, 2004.

[13]  Dean M. Tullsen,et al.  Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[14]  Chen-Yi Lee,et al.  A high throughput low cost context-based adaptive arithmetic codec for multiple standards , 2002, Proceedings. International Conference on Image Processing.

[15]  Richard G. Lyons.  JPEG2000Choices and Tradeoffs for Encoders , 2007 .

[16]  Andreas Uhl,et al.  Parallel JPEG2000 image coding on multiprocessors , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[17]  Michael W. Marcellin,et al.  JPEG2000 - image compression fundamentals, standards and practice , 2002, The Kluwer International Series in Engineering and Computer Science.

[18]  Samuel Williams,et al.  The Landscape of Parallel Computing Research: A View from Berkeley , 2006 .

[19]  Takao Onoye,et al.  Design framework for JPEG2000 encoding system architecture , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[20]  Liang-Gee Chen,et al.  High speed memory efficient EBCOT architecture for JPEG2000 , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[21]  Chaitali Chakrabarti,et al.  A high performance JPEG2000 architecture , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[22]  S. Nooshabadi,et al.  High speed VLSI architecture for bit plane encoder of JPEG2000 , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..