Networks on Chips: A New Paradigm for Component-Based MPSoC Design

Publisher Summary This chapter addresses a methodology for the design of the interconnection among components that satisfies the needs for modular and robust design, under the constraints provided by the physical interconnect. It reviews the challenges of designing systems-on-chips (SoCs) with tens or hundreds of processing elements in 100 to 25 nm silicon technologies. These challenges include dealing with design complexity and providing reliable, high-performance operation with a small energy consumption. The modular, component-based design of both hardware and software is needed to design complex SoCs. Efficient communication on SoCs can be achieved by reconfigurable micronetworks whose layered design can exploit methods and tools used for general networks. SoCs differ from wide-area networks because of local proximity, and because they are much more predictable at design time. Network design is influenced by many design metrics. Both micronetwork and general network design must meet the performance requirements. The chapter also analyzes different layers in micronetwork design and outlines the corresponding research problems.

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