10Gbps decision feedback equalizer with dynamic lookahead decision loop
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[1] Keshab K. Parhi,et al. Parallel adaptive decision feedback equalizers , 1993, IEEE Trans. Signal Process..
[2] Keshab K. Parhi. Design of multigigabit multiplexer-loop-based decision feedback equalizers , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] Markku Renfors,et al. The maximum sampling rate of digital filters under hardware speed constraints , 1981 .
[4] Teresa H. Y. Meng,et al. A robust adaptive parallel DFE using extended LMS , 1993, IEEE Trans. Signal Process..
[5] S. Gowda,et al. A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.
[6] Shyh-Jye Jou,et al. Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[7] Keshab K. Parhi,et al. Low Complexity Design of High Speed Parallel Decision Feedback Equalizers , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).
[8] Keshab K. Parhi,et al. Pipelining of parallel multiplexer loops and decision feedback equalizers , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[9] Teresa H. Meng,et al. High sampling rate adaptive decision feedback equalizers , 1990, International Conference on Acoustics, Speech, and Signal Processing.
[10] An-Yeu Wu,et al. High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[11] John M. Cioffi,et al. Vector coding with decision feedback equalization for partial response channels , 1988, IEEE Global Telecommunications Conference and Exhibition. Communications for the Information Age.
[12] C.A. Belfiore,et al. Decision feedback equalization , 1979, Proceedings of the IEEE.