On the communication capability of the self-reconfigurable gate array architecture

The self-reconfigurable gate array (SRGA) architecture consists of an array of processing elements connected by row and column trees. In this paper, we study the communication capability of this interconnection fabric. We derive a necessary condition for any set of k one-to-one communications to be performed in t steps, for any 1 ? t ? k. Next we identify a property of the communication set, called partitionability, for which this necessary condition is sufficient as well. Then we show two classes of communication sets to possess this property. As a special case of one of these results, we show that the set of 1-step communications of a segmentable bus requires at most two steps on the SRGA architecture. This result implies that the communication ability of the bit model HV-R-Mesh, a special case of the bit model R-Mesh, can be emulated by the SRGA architecture without signifficant overhead.

[1]  F. Leighton,et al.  Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes , 1991 .

[2]  John J. Murray,et al.  A Mathematical Benefit Analysis of Context Switching Reconfigurable Computing , 1998, IPPS/SPDP Workshops.

[3]  Sajal K. Das,et al.  Book Review: Introduction to Parallel Algorithms and Architectures : Arrays, Trees, Hypercubes by F. T. Leighton (Morgan Kauffman Pub, 1992) , 1992, SIGA.

[4]  David Peleg,et al.  The Complexity of Reconfiguring Network Models , 1992, Inf. Comput..

[5]  Michael J. Wirthlin,et al.  DISC: the dynamic instruction set computer , 1995, Optics East.

[6]  Ramachandran Vaidyanathan,et al.  On the Power of Segmenting and Fusing Buses , 1996, J. Parallel Distributed Comput..

[7]  Reiner W. Hartenstein,et al.  On Reconfigurable Co-processing Units , 1998, IPPS/SPDP Workshops.

[8]  Viktor K. Prasanna,et al.  Hardware Object Selection for Mapping Loops onto Reconfigurable Architectures , 1999, PDPTA.

[9]  Koji Nakano,et al.  A Bibliography of Published Papers on Dynamically Reconfigurable Architectures , 1995, Parallel Process. Lett..

[10]  Viktor K. Prasanna,et al.  String matching on multicontext FPGAs using self-reconfiguration , 1999, FPGA '99.

[11]  James A. Anderson,et al.  Discrete Mathematics with Combinatorics , 2000 .

[12]  Viktor K. Prasanna,et al.  Genetic Programming Using Self-Reconfigurable FPGAs , 1999, FPL.

[13]  Viktor K. Prasanna,et al.  A Self-Reconfigurable Gate Array Architecture , 2000, FPL.