Accelerating functional verification of PCI express endpoint by emulating host system using PCI express core

PCI Express is a high-performance I/O bus protocol. The PCI Express protocol provides higher bandwidth than the legacy buses that makes PCI Express as an ideal choice for a wide variety of applications such as Network Interface, Graphics Accelerators, and Storage Controllers (SSD). The PCI Express protocol supports many features to improve performance of I/O Bus, so verification of a design based on this protocol is a very long and time consuming process. As an application based on the PCI Express protocol becomes more and more complex the verification complexity increases many folds. PCI Express Endpoint device communicates with the host (Processor/Memory) using the Host Interface logic. This logic plays a vital role as it can affect the overall performance of the Endpoint device. The Host Interface logic is protocol specific and responsible for the data transfer from host to device and vice versa. Strategically, as this logic is very crucial, it has to be verified properly. There are multiple ways to verify the host interface logic. However, there is a trade-off between design development time (including verification time) and overall cost. In this paper we present a novel approach to verify the Host Interface Logic. Our method uses a PCI Express core that will act as the Root Complex connected to the Host Interface Logic, i.e. Design Under Test (DUT), this will help to minimize overall design development time by reducing verification time.