Layout-driven detection of bridge faults in interconnects

This paper presents a new approach to fault detection of interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults by a novel weighted graph approach. This graph is then analyzed to appropriately schedule the order of test compaction and execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weights of the new adjacency graph as figure of merit. The advantage of the proposed approach is that on average, early detection of faults is possible using a number of tests significantly smaller than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still requiring a small number of vectors.

[1]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[2]  Paul Wagner,et al.  INTERCONNECT TESTING WITH BOUNDARY SCAN , 1987 .

[3]  Vinod K. Agarwal,et al.  Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[4]  Wojciech Maly,et al.  Layout-driven test generation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Hua Xue,et al.  A net-oriented method for realistic fault analysis , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[6]  Fabrizio Lombardi,et al.  A row-based FPGA for single and multiple stuck-at fault detection , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

[7]  Fabrizio Lombardi,et al.  A new diagnosis approach for short faults in interconnects , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[8]  Tong Liu,et al.  Diagnosis of interconnects and FPICs using a structured walking-1 approach , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[9]  M. Rivier,et al.  Approximation of critical area of ICs with simple parameters extracted from the layout , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

[10]  W. Kent Fuchs,et al.  Optimal interconnect diagnosis of wiring networks , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Fabrizio Lombardi,et al.  A Sweeping Line Approach to Interconnect Testing , 1996, IEEE Trans. Computers.