PoliCym: Rapid Prototyping of Resource Management Policies for HMPs

Heterogeneous Multiprocessors (HMPs) are becoming pervasive in current modern embedded platforms (e.g. mobile devices). These platforms often provide better power-performance tradeoffs than their homogeneous predecessors; however, novel and intelligent resource management policies are required to manage the added complexity of heterogeneous platforms and exploit their power-performance benefits. In this paper we propose PoliCym, a framework for the prototyping, validating, and deploying resource management policies for heterogeneous platforms. PoliCym provides two main benefits to resource management policy developers and to the research community: 1) a trace-based offline simulator allows policies to be quickly prototyped, debugged, and validated on top of arbitrary platform configurations; and 2) a light-weight sensing-actuation interface allows the same policies to be efficiently deployed on top of Linux-based systems without the need for implementation changes or additional development cycles. We evaluate our light-weight interface in terms of overhead and validate the PoliCym offline simulator for an ARM big.LITTLE based HMP platform running Linux.

[1]  Jung Ho Ahn,et al.  The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing , 2013, TACO.

[2]  Tong Li,et al.  LinSched: The Linux Scheduler Simulator , 2008, ISCA PDCCS.

[3]  Alexandra Fedorova,et al.  AKULA: A toolset for experimenting and developing thread placement algorithms on multicore systems , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

[4]  Muhammad Shafique,et al.  Hayat: Harnessing Dark Silicon and variability for aging deceleration and balancing , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[6]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[7]  Lieven Eeckhout,et al.  Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[8]  Mahmut T. Kandemir,et al.  REEact: a customizable virtual execution manager for multicore platforms , 2012, VEE '12.

[9]  Nikil D. Dutt,et al.  SPARTA: Runtime task allocation for energy efficient heterogeneous manycores , 2016, 2016 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[10]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[11]  Carole-Jean Wu,et al.  A study of mobile device utilization , 2015, 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[12]  Tor M. Aamodt,et al.  Modeling Cache Contention and Throughput of Multiprogrammed Manycore Processors , 2012, IEEE Transactions on Computers.

[13]  Heba Khdr,et al.  Scalable probabilistic power budgeting for many-cores , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[14]  Diana Marculescu,et al.  Procrustes1: Power Constrained Performance Improvement Using Extended Maximize-Then-Swap Algorithm , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Aamer Jaleel,et al.  CMPSched$im: Evaluating OS/CMP interaction on shared cache management , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[16]  Lieven Eeckhout,et al.  Undersubscribed threading on clustered cache architectures , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[17]  O Seongil,et al.  McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[18]  Nikil D. Dutt,et al.  Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile Platforms , 2017, IEEE Transactions on Multi-Scale Computing Systems.

[19]  Vanchinathan Venkataramani,et al.  Hierarchical power management for asymmetric multi-core in dark silicon era , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[20]  Nikil D. Dutt,et al.  Run-DMC: Runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency , 2015, 2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[21]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures for multithreaded workload performance , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[22]  LiSheng,et al.  The McPAT Framework for Multicore and Manycore Architectures , 2013 .

[23]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[24]  Lieven Eeckhout,et al.  Scheduling heterogeneous multi-cores through performance impact estimation (PIE) , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).