Macro-based hardware compilation of Java/sup TM/ bytecodes into a dynamic reconfigurable computing system
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[1] G. De Micheli,et al. SpC: synthesis of pointers in C application of pointer analysis to the behavioral synthesis from C , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[2] J.M.P. Cardoso,et al. Towards an automatic path from Java/sup TM/ bytecodes to hardware through high-level synthesis , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).
[3] Viktor K. Prasanna,et al. Seeking Solutions in Configurable Computing , 1997, Computer.
[4] Hideharu Amano,et al. WASMII: a data driven computer on a virtual hardware , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.
[5] Ranga Vemuri,et al. An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures , 1998, IPPS/SPDP Workshops.
[6] Rajesh Gupta,et al. Hardware/software co-design , 1996, Proc. IEEE.
[7] Harvey F. Silverman,et al. Processor reconfiguration through instruction-set metamorphosis , 1993, Computer.
[8] Steven S. Muchnick,et al. Advanced Compiler Design and Implementation , 1997 .
[9] João MP Cardoso. Towards an Automatic Path from Java Bytecodes to Hardware Through High-Level Synthesis 1 , 1998 .
[10] Reiner W. Hartenstein,et al. Parallelization in Co-Compilation for Configurable Accelerators. , 1998 .
[11] Joe D. Warren,et al. The program dependence graph and its use in optimization , 1987, TOPL.
[12] Ranga Vemuri,et al. Optimal temporal partitioning and synthesis for reconfigurable architectures , 1998, Proceedings Design, Automation and Test in Europe.
[13] Minh N. Do,et al. Youn-Long Steve Lin , 1992 .
[14] Dinesh Bhatia,et al. Temporal partitioning and scheduling for reconfigurable computing , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).
[15] M AthanasPeter,et al. Processor reconfiguration through instruction-set metamorphosis , 1993 .
[16] Frank Yellin,et al. The Java Virtual Machine Specification , 1996 .
[17] Louise Trevillyan,et al. Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[18] Peter M. Athanas,et al. Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[19] Giovanni De Micheli,et al. SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C , 1998, ICCAD.
[20] Giovanni De Micheli,et al. Synthesis and Optimization of Digital Circuits , 1994 .
[22] Alfred V. Aho,et al. Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.
[23] Milan Vasilko,et al. Architectural Synthesis Techniques for Dynamically Reconfigurable Logic , 1996, FPL.
[24] Daniel D. Gajski,et al. High ― Level Synthesis: Introduction to Chip and System Design , 1992 .