SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells

Embedded Flash NVM has become a key component in many applications, such as data processing, industrial electronics, automotive electronics, consumer electronics and wireless communications. SuperFlash® technology is based on the split-gate concept, using source-side electron injection for programming. The aim of this work is to propose, for the first time, a SPICE macro-model of the 2T (Select Gate and Floating Gate) 3rd generation SuperFlash cell [Hidaka], implemented in a 55 nm CMOS technology. A parameter extraction procedure is also proposed, showing a good agreement between the model and measurements.

[1]  Hideto Hidaka.  Evolution of embedded flash memory technology for MCU , 2011, 2011 IEEE International Conference on IC Design & Technology.

[2]  Yuri Tkachev,et al.  Generation of single-and double-charge electron traps in tunnel oxide of flash memory cells under Fowler-Nordheim stress , 2011, 2011 IEEE International Integrated Reliability Workshop Final Report.