The Effect of Negative Feedback on Single Event Transient Propagation in Digital Circuits
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B. Narasimham | B.L. Bhuva | R.D. Schrimpf | A.F. Witulski | W.T. Holman | L.W. Massengill | W.H. Robinson | W. H. Robinson | peixiong zhao | L. Massengill | B. Narasimham | B. Bhuva | A. Witulski | W. Holman
[1] Avinoam Kolodny,et al. Crosstalk noise reduction in synthesized digital logic circuits , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[2] Antonio J. Acosta,et al. Logical modelling of delay degradation effect in static CMOS gates , 2000 .
[3] M. Baze,et al. Attenuation of single event induced pulses in CMOS combinational logic , 1997 .
[4] Mark Horowitz,et al. Timing Models for MOS Circuits , 1983 .
[5] P. Hazucha,et al. Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .
[6] V. Srinivasan,et al. Single-event mitigation in combinational logic using targeted data path hardening , 2005, IEEE Transactions on Nuclear Science.
[7] P. Eaton,et al. Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
[8] Ronald R. Troutman,et al. Latchup in CMOS Technology: The Problem and Its Cure , 1986 .
[9] Lorenzo Alvisi,et al. Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.
[10] Ronald R. Troutman. Latchup in CMOS Technology , 1986 .