Design of High Precision and High Consistency Bandgap in 65nm CMOS

High precision and consistency band gap references are of great importance in mass production. However, in deep sub-micron process, inevitable deterioration will be introduced during layout design and chip fabrication. This paper analyzes the possible causes and concludes some dedicated solutions applicable in band gap design, including digital aided trimming, layout optimization and Monte Carlo simulation. Besides, in order to verify the effect of Monte Carlo simulation, two versions of band gap circuits with and without the simulation have been implemented in 65nm CMOS process. Their samples are compared and analyzed. Measurement results show that the proposed techniques can bring significant improvement on output precision and consistency. The bias offset is able to be kept within 6.8% from its normal value before calibration and 1.72% after digital trimming. In addition, the temperature variation is 7 ppm/°C.