Overview of nano-electronics printing techniques and patterning defects detection

The art and science of lithography has come a long way supporting the semiconductor manufacturing. In this paper the recent trend in semiconductor lithography has been reviewed along with the discussion of present day technological challenges and various efforts that are being made to stretch the knowhow for manufacturing next advanced node. The layout features undergo transformation through the manufacturing processes with adverse changes at times that affects the functionality of the chip. Several design verification checks have been used in the industry to detect these "hotspots" and resolution enhancement techniques try to mitigate some of these risks. Two such layout verification methods have also been discussed in this review paper with example layout features to explain model based simulation and Voronoi tessellation method.

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