Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability

Abstract In the present paper, a two-dimensional (2-D) analytical model for graded channel fully depleted cylindrical/surrounding gate MOSFET (GC FD CGT/SGT) has been developed by solving the Poisson’s equation in cylindrical coordinates. An abrupt transition of silicon film doping at the interface has been assumed and the effects of the doping and the lengths of the high and low doped regions have been taken into account. The model is used to obtain the expressions of surface potential and electric field in the two regions. The analysis is extended to obtain the expressions for threshold voltage (Vth) and subthreshold swing. It is shown that a graded doping profile in the channel leads to suppression of short channel effects (SCEs) like threshold voltage roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. The results so obtained have been compared with simulated results obtained using the device simulator ATLAS 3D and are found to be in good agreement.

[1]  Denis Flandre,et al.  Analog performance and application of graded-channel fully depleted SOI MOSFETs , 2000 .

[2]  S. Banerjee,et al.  Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping , 2002 .

[3]  Jean-Pierre Raskin,et al.  An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics , 2002 .

[4]  S. Maegawa,et al.  A Vertical /spl Phi/-shape Transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond , 1994, Proceedings of 1994 VLSI Technology Symposium.

[5]  Fumio Horiguchi,et al.  Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits , 1991 .

[6]  S. Odanaka,et al.  Potential design and transport property of 0.1-/spl mu/m MOSFET with asymmetric channel profile , 1997 .

[7]  Fumio Horiguchi,et al.  Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's , 1991 .

[8]  K. K. Young.  Short-channel effect in fully depleted SOI MOSFETs , 1989 .

[9]  D. Monroe,et al.  Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs , 2000, IEEE Electron Device Letters.

[10]  G. Baccarani,et al.  A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects , 1999 .

[11]  Mark S. Lundstrom,et al.  The ballistic nanotransistor: a simulation study , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[12]  Juan Bautista Roldán,et al.  Study of the effects of a stepped doping profile in short-channel MOSFETs , 1997 .

[13]  Hideaki Arima,et al.  Source-to-drain nonuniformly doped channel (NUDC) MOSFET structures for high current drivability and threshold voltage controllability , 1992 .

[14]  Hyungsoon Shin,et al.  An 0.1-/spl mu/m asymmetric halo by large-angle-tilt implant (AHLATI) MOSFET for high performance and reliability , 1999 .

[15]  Fumio Horiguchi,et al.  A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's , 1995 .

[16]  Abhinav Kranti,et al.  Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET , 2001 .

[17]  Denis Flandre,et al.  A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation , 2005 .

[18]  Baohong Cheng,et al.  Exploration of velocity overshoot in a high-performance deep sub-0.1-μm SOI MOSFET with asymmetric channel profile , 1999, IEEE Electron Device Letters.

[19]  Abhinav Kranti,et al.  Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications , 2004 .

[20]  J. Plummer,et al.  Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's , 1997, IEEE Electron Device Letters.

[21]  Y. Naveh,et al.  Modeling of 10-nm-scale ballistic MOSFET's , 2000, IEEE Electron Device Letters.

[22]  Denis Flandre,et al.  Analog circuit design using graded-channel silicon-on-insulator nMOSFETs , 2002 .

[23]  Abhinav Kranti,et al.  Design and optimization of thin film fully depleted vertical surrounding gate (VSG) MOSFETs for enhanced short channel immunity , 2002 .

[24]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[25]  F. Masuoka,et al.  NAND-type DRAM-on-SGT , 2005, IEEE Transactions on Electron Devices.

[26]  H. A. Hamid,et al.  Explicit continuous model for long-channel undoped surrounding gate MOSFETs , 2005, IEEE Transactions on Electron Devices.

[27]  Abhinav Kranti,et al.  Design and optimization of vertical surrounding gate MOSFETs for enhanced transconductance-to-current ratio (gm/Ids) , 2003 .