SOI technology: An opportunity for RF designers?

This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications, reaching cutoff frequencies close to 500 GHz. SOI also presents the major advantage of providing high resistivity substrate capabilities, leading to substantially reduced substrate RF losses. High Resistivity SOI is commonly foreseen as a promising substrate for radio frequency integrated circuits and mixed signal applications. In this paper, based on several experimental and simulation results, the interest, limitations but also possible future improvements of the SOI MOS technology are presented.

[1]  Ph. Benech,et al.  State of the art 200 GHz passive components and circuits integrated in advanced thin SOI CMOS technology on High Resistivity substrate , 2006, 2006 IEEE international SOI Conferencee Proceedings.

[2]  D. Lederer,et al.  New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity , 2005, IEEE Electron Device Letters.

[3]  P. Bai,et al.  A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications , 2006, 2006 International Electron Devices Meeting.

[4]  W. Baechtold,et al.  Si and GaAs 0.5 μm-gate Schottky-barrier field-effect transistors , 1973 .

[5]  P. Ho,et al.  W-band high efficiency InP-based power HEMT with 600 GHz fmax , 1995 .

[6]  W. Deal,et al.  Sub 50 nm InP HEMT Device with Fmax Greater than 1 THz , 2007, 2007 IEEE International Electron Devices Meeting.

[7]  J. Raskin,et al.  High resistivity SOI substrates: how high should we go? , 2003, 2003 IEEE International Conference on SOI.

[8]  Akira Matsuzawa,et al.  Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications , 2006 .

[9]  K. Ohuchi,et al.  Impact of BOX scaling on 30 nm gate length FD SOI MOSFET , 2005, 2005 IEEE International SOI Conference Proceedings.

[10]  F. Danneville,et al.  RF Small-Signal Analysis of Schottky-Barrier p-MOSFET , 2008, IEEE Transactions on Electron Devices.

[11]  G. Pailloncy,et al.  Static and High-Frequency Behavior and Performance of Schottky-Barrier p-MOSFET Devices , 2007, IEEE Transactions on Electron Devices.

[12]  O. Faynot,et al.  Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel , 2010 .

[13]  E. Nowak,et al.  High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[14]  Vincent Fusco,et al.  SiO/sub 2/ interface layer effects on microwave loss of high-resistivity CPW line , 1999 .

[15]  Frédéric Boeuf,et al.  Impact of strained-channel n-MOSFETs with a SiGe virtual substrate on dielectric interface quality evaluated by low frequency noise measurements , 2007, Microelectron. Reliab..

[16]  B. Rejaei,et al.  Surface-passivated high-resistivity silicon substrates for RFICs , 2004, IEEE Electron Device Letters.

[17]  F. Gianesello,et al.  1.8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS Technology , 2007, 2007 IEEE/MTT-S International Microwave Symposium.

[18]  T. Mimura,et al.  A New Field-Effect Transistor with Selectively Doped GaAs/n-AlxGa1-xAs Heterojunctions , 1980 .

[19]  A. Vandooren,et al.  Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions , 2003, IEEE International Electron Devices Meeting 2003.

[20]  K. F. Lee,et al.  Impact of distributed gate resistance on the performance of MOS devices , 1994 .

[21]  Tah-Hsiung Chu,et al.  The thru-line-symmetry (TLS) calibration method for on-wafer scattering matrix measurement of four-port networks , 2004, 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535).

[22]  B. Jagannathan,et al.  Record RF performance of 45-nm SOI CMOS Technology , 2007, 2007 IEEE International Electron Devices Meeting.

[23]  J.-P. Raskin,et al.  Wide-Band Simulation and Characterization of Digital Substrate Noise in SOI Technology , 2007, 2007 IEEE International SOI Conference.

[24]  M. Ostling,et al.  Control of Self-Heating in Thin Virtual Substrate Strained Si MOSFETs , 2006, IEEE Transactions on Electron Devices.

[25]  S. Shue,et al.  Low capacitance approaches for 22nm generation Cu interconnect , 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

[26]  Michael Dydyk,et al.  Coplanar waveguides and microwave inductors on silicon substrates , 1995 .

[27]  Mark J. W. Rodwell,et al.  Submicron scaling of HBTs , 2001 .

[28]  S. C. Wang,et al.  W-band high efficiency InP-based power HEMT with 600 GHz f/sub max/ , 1995 .

[29]  F. Gianesello,et al.  On the Design of High Performance RF Integrated Inductors on High Resistively Thin Film 65 nm SOI CMOS Technology , 2008, 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[30]  Kah-Wee Ang,et al.  Strained ${\rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance , 2008, IEEE Transactions on Electron Devices.

[31]  W. Lee,et al.  A novel CVD-SiBCN Low-K spacer technology for high-speed applications , 2008, 2008 Symposium on VLSI Technology.

[32]  Jean-Pierre Colinge,et al.  Silicon-on-insulator 'gate-all-around' MOS device , 1990, 1990 IEEE SOS/SOI Technology Conference. Proceedings.

[33]  K. Steinhubl.  Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[34]  Carver A. Mead,et al.  Schottky barrier gate field effect transistor , 1966 .

[35]  J. Costa,et al.  Linear cellular antenna switch for highly-integrated SOI front-end , 2007, 2007 IEEE International SOI Conference.

[36]  J. Raskin,et al.  Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling , 1998 .

[37]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[38]  Kamel Benaissa,et al.  RF CMOS on high-resistivity substrates for system-on-chip applications , 2003 .

[39]  Marc van Heijningen,et al.  High-level simulation of substrate noise generation including power supply noise coupling , 2000, Proceedings 37th Design Automation Conference.

[40]  Denis Flandre,et al.  Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .

[41]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[42]  Sorin Cristoloveanu,et al.  Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture , 2002 .

[43]  F. Danneville,et al.  Low Temperature Implementation of Dopant-Segregated Band-edge Metallic S/D junctions in Thin-Body SOI p-MOSFETs , 2007, 2007 IEEE International Electron Devices Meeting.

[44]  E. Morifuji,et al.  High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs , 1996, International Electron Devices Meeting. Technical Digest.

[45]  Denis Flandre,et al.  FinFET analogue characterization from DC to 110 GHz , 2005 .

[46]  J. Raskin,et al.  Bias effects on RF passive structures in HR Si substrates , 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[47]  K. Jenkins,et al.  Experimental analysis of the effect of substrate noise on PLL performance , 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[48]  B. Riccò,et al.  Characterization of polysilicon-gate depletion in MOS structures , 1996, IEEE Electron Device Letters.

[49]  H. De Man,et al.  Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[50]  B. Iniguez,et al.  Finite Element Simulations of Parasitic Capacitances Related to Multiple-Gate Field-Effect Transistors Architectures , 2008, 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[51]  Sorin Cristoloveanu,et al.  Silicon on insulator technologies and devices: from present to future , 2001 .

[52]  V. Kilchytska,et al.  Perspective of FinFETs for analog applications , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[53]  J.-P. Raskin,et al.  Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization , 2006, IEEE Transactions on Electron Devices.

[54]  O. Faynot,et al.  0.25 μm fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters , 2002 .

[55]  Jean-Pierre Raskin,et al.  High-frequency performance of Schottky Barrier p-MOSFET devices , 2008 .

[56]  H. F. Cooke,et al.  Microwave transistors: Theory and design , 1971 .

[57]  Mansun Chan,et al.  Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs , 2007, IEEE Transactions on Electron Devices.

[58]  G. Pailloncy,et al.  High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices , 2008, IEEE Electron Device Letters.

[59]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs: device design guidelines , 2002 .

[60]  Denis Flandre,et al.  Transconductance and mobility behaviors in UTB SOI MOSFETs with standard and thin BOX , 2009 .

[61]  Jean-Pierre Raskin,et al.  Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs , 2004 .

[62]  J. Larson,et al.  Overview and status of metal S/D Schottky-barrier MOSFET technology , 2006, IEEE Transactions on Electron Devices.

[63]  V. Fusco,et al.  Low-loss CPW lines on surface stabilized high-resistivity silicon , 1999, IEEE Microwave and Guided Wave Letters.

[64]  J.-P. Raskin,et al.  High-Frequency Noise Performance of 60-nm Gate-Length FinFETs , 2008, IEEE Transactions on Electron Devices.

[65]  Byung-Gook Park,et al.  Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile , 2002 .

[66]  J. Raskin,et al.  Effective resistivity of fully-processed SOI substrates , 2005 .

[67]  W. Heinrich,et al.  Quasi-TEM description of MMIC coplanar lines including conductor-loss effects , 1993 .

[68]  Denis Flandre,et al.  Substrate crosstalk reduction using SOI technology , 1997 .

[69]  P. Wambacq,et al.  Analysis and experimental verification of digital substrate noise generation for epi-type substrates , 2000, IEEE Journal of Solid-State Circuits.

[70]  Solid-State Electronics , 1955, Nature.

[71]  Georges Gielen,et al.  Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies , 2003, IEEE J. Solid State Circuits.

[72]  Cristian Andrei,et al.  Impact of low-frequency substrate disturbances on a 4.5GHz VCO , 2006, Microelectron. J..

[73]  N. Fel,et al.  A New Approach for SOI Devices Small-Signal Parameters Extraction , 2000 .

[74]  F. Danneville,et al.  What are the limiting parameters of deep-submicron MOSFETs for high frequency applications? , 2003, IEEE Electron Device Letters.

[75]  E. Kasper,et al.  Attenuation mechanisms of aluminum millimeter-wave coplanar waveguides on silicon , 2003 .