Test metrics for analog parametric faults
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[1] R. Voorakaranam,et al. Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis , 1997, Proceedings International Test Conference 1997.
[2] Helmut Graeb,et al. Design based analog testing by characteristic observation inference , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[3] Wieslaw Kuzmicz,et al. Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[4] João Paulo Teixeira,et al. Defect level evaluation in an IC design environment , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Stephen W. Director,et al. The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] B. Kaminska,et al. Oscillation-test strategy for analog and mixed-signal integrated circuits , 1996, Proceedings of 14th VLSI Test Symposium.
[7] Zhihua Wang,et al. An efficient yield optimization method using a two step linear approximation of circuit performance , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[8] Bozena Kaminska,et al. LIMSoft: automated tool for design and test integration of analog circuits , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[9] Brown,et al. Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.
[10] Claude Abraham,et al. Fault simulation for mixed-signal systems , 1996, J. Electron. Test..
[11] Alberto L. Sangiovanni-Vincentelli,et al. Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..