FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation

PCT No. PCT/JP97/01279 Sec. 371 Date Dec. 8, 1997 Sec. 102(e) Date Dec. 8, 1997 PCT Filed Apr. 10, 1997 PCT Pub. No. WO97/38285 PCT Pub. Date Oct. 16, 1997A measure obtained by a counting circuit (2) is converted by a processing circuit (3) to an indication angle signal at a predetermined conversion cycle. A smoothing circuit (4) comprises a division circuit (11) for calculating the difference between the previous indication angle data theta 0 and the present indication angle data theta 1 which is outputted after the conversion cycle T and has changed, and sequentially accumulating the angle data corresponding to T/n (where n is an integer of 2 or more) shorter than the conversion cycle T at a division cycle T/n and a voltage memory (12) for converting and outputting a two-phase driving signal for driving a stepper motor type measuring instrument (6) on the basis of the indication angle data theta i outputted from the division circuit (11) every division cycle T/n. A voltage signal is generated through an output circuit (5) for converting the signal to a voltage signal to be applied to a two-phase excitation coil of a stepper motor. This voltage signal drives the stepper type motor measuring instrument (6) and rotates a pointer (9) fixed to the end of a driving shaft at angle indication corresponding to a scale (8) of a dial (7).