A data-dependent energy reduction algorithm for SAR ADC using self-adaptive window

Abstract A new data-dependent energy reduction algorithm for successive approximation register (SAR) analog-to-digital convert (ADC) is presented in this paper. The proposed algorithm starts with a less significant bit (LSB) window with N-bit length, which is configurable depending on signal characteristics. By using less significant bit to more significant bit (L2M) successive extending (SE), the signal window is self-adaptive to cover the input signal within boundary. The proposed technique leads to less mean bit trials per sample, suggesting higher energy efficiency in many data-dependant ADC applications. Furthermore, this algorithm can be implemented based on conventional charge redistribution SAR ADC without any change in analog circuits. According to MATLAB simulation, the proposed technique is able to reduce mean bit trials effectively in biomedical signal detection applications. The simulation results show 37.9%, 32.3% and 18.2% less mean bit trials than using conventional SAR algorithm in processing electrocardiogram (ECG), electroencephalogram (EEG) and in electro-myography (EMG) signals respectively.

[1]  Hsin-Shu Chen,et al.  A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS , 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[2]  Arthur H. M. van Roermund,et al.  A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step , 2013, IEEE Journal of Solid-State Circuits.

[3]  Zhichao Tan,et al.  An Adaptive SAR ADC for DC to Nyquist Rate Signals , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[4]  Marian Verhelst,et al.  Predictive sensing in analog-to-digital converters for biomedical applications , 2013, International Symposium on Signals, Circuits and Systems ISSCS2013.

[5]  Ameya Bhide,et al.  A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-$\mu$m CMOS for Medical Implant Devices , 2012, IEEE Journal of Solid-State Circuits.

[6]  Refet Firat Yazicioglu,et al.  A 30 $\mu$ W Analog Signal Processor ASIC for Portable Biopotential Signal Monitoring , 2011, IEEE Journal of Solid-State Circuits.

[7]  Anantha Chandrakasan,et al.  A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First Successive Approximation , 2014, IEEE Journal of Solid-State Circuits.

[8]  Zhangming Zhu,et al.  A charge-sharing switching scheme for SAR ADCs in biomedical applications , 2018, Microelectron. J..

[9]  Soon-Jyh Chang,et al.  A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications , 2012, IEEE Journal of Solid-State Circuits.

[10]  Suhwan Kim,et al.  Power efficient SAR ADC adaptive to input activity for ECG monitoring applications , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[11]  Nan Sun,et al.  Predicting ADC: A new approach for low power ADC design , 2014, 2014 IEEE Dallas Circuits and Systems Conference (DCAS).

[12]  Ning Ning,et al.  Predictive SAR ADC with two-step loading technology for energy reduction , 2019, Microelectron. J..

[13]  Franco Maloberti,et al.  A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[14]  Soon-Jyh Chang,et al.  A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[15]  G.B. Moody,et al.  The impact of the MIT-BIH Arrhythmia Database , 2001, IEEE Engineering in Medicine and Biology Magazine.

[16]  Michael P. Flynn,et al.  A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC , 2015, IEEE Journal of Solid-State Circuits.