Nonlinear compensation for finite word length effects of an LMS echo canceller algorithm suitable for VLSI implementation
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When an algorithm for echo cancellation is to be implemented in VLSI, it is essential to minimize the word length of the coefficients for economical reasons. While insufficient word length significantly degrades the performance of the canceller, it is possible to compensate for its effects by using a nonuniform number representation system, i.e. pseudo-floating-point arithmetic. Such an algorithm, using 10 bits, is discussed and its performance is compared with that of ordinary fixed-point algorithms with various number of bits. A multichannel echo-canceller chip has been built using this algorithm. It is used successfully in a T1 echo canceller system.<<ETX>>
[1] Donald L. Duttweiler,et al. A Cascadable VLSI Echo Canceller , 1984, IEEE Journal on Selected Areas in Communications.
[2] D. Duttweiler,et al. A single-chip VLSI echo canceler , 1980, The Bell System Technical Journal.
[3] K. Shenoi,et al. An echo canceller with 6-channel capability , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.
[4] D. Lin,et al. Echo cancellation algorithms , 1984, IEEE ASSP Magazine.