Nonlinear compensation for finite word length effects of an LMS echo canceller algorithm suitable for VLSI implementation

When an algorithm for echo cancellation is to be implemented in VLSI, it is essential to minimize the word length of the coefficients for economical reasons. While insufficient word length significantly degrades the performance of the canceller, it is possible to compensate for its effects by using a nonuniform number representation system, i.e. pseudo-floating-point arithmetic. Such an algorithm, using 10 bits, is discussed and its performance is compared with that of ordinary fixed-point algorithms with various number of bits. A multichannel echo-canceller chip has been built using this algorithm. It is used successfully in a T1 echo canceller system.<<ETX>>

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