Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure

This study focuses on the use of genetic programming to automate the design of robust analog circuits. We define two complementary types of failure modes: partial short-circuit and partial disconnect, and demonstrated novel circuits that are resilient across a spectrum of fault levels. In particular, we focus on designs that are uniformly robust, and unlike designs based on redundancy, do not have any single point of failure. We also explore the complementary problem of designing tamper-proof circuits that are highly sensitive to any change or variation in their operating conditions. We find that the number of components remains similar both for robust and standard circuits, suggesting that the robustness does not necessarily come at significant increased circuit complexity. A number of fitness criteria, including surrogate models and co-evolution were used to accelerate the evolutionary process. A variety of circuit types were tested, and the practicality of the generated solutions was verified by physically constructing the circuits and testing their physical robustness.

[1]  Jon B. Hagen,et al.  Radio-Frequency Electronics: Circuits and Applications , 1996 .

[2]  John R. Koza,et al.  Automated synthesis of analog electrical circuits by means of genetic programming , 1997, IEEE Trans. Evol. Comput..

[3]  Jason D. Lohn,et al.  Automated Analog Circuit Sythesis Using a Linear Representation , 1998, ICES.

[4]  J. B. Grimbleby,et al.  Hybrid genetic algorithms for analogue network synthesis , 1999, Proceedings of the 1999 Congress on Evolutionary Computation-CEC99 (Cat. No. 99TH8406).

[5]  Adrian Stoica,et al.  Fault-tolerant evolvable hardware using field-programmable transistor arrays , 2000, IEEE Trans. Reliab..

[6]  Hitoshi Iba,et al.  Analog circuit design with a variable length chromosome , 2000, Proceedings of the 2000 Congress on Evolutionary Computation. CEC00 (Cat. No.00TH8512).

[7]  Paul J. Layzell,et al.  Understanding Inherent Qualities of Evolved Circuits: Evolutionary History as a Predictor of Fault Tolerance , 2000, ICES.

[8]  Marley M. B. R. Vellasco,et al.  Evolvable hardware: on the automatic synthesis of analog control systems , 2000, 2000 IEEE Aerospace Conference. Proceedings (Cat. No.00TH8484).

[9]  Yun Li,et al.  GA automated design and synthesis of analog circuits with practical constraints , 2001, Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No.01TH8546).

[10]  Christofer Toumazou,et al.  The invention of CMOS amplifiers using genetic programming and current-flow analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Heinz Mühlenbein,et al.  A Comparison of Different Circuit Representations for Evolutionary Analog Circuit Design , 2003, ICES.

[12]  Principles in the Evolutionary Design of Digital Circuits—Part I , 2004, Genetic Programming and Evolvable Machines.

[13]  Julian Francis Miller,et al.  Principles in the Evolutionary Design of Digital Circuits—Part II , 2000, Genetic Programming and Evolvable Machines.

[14]  John R. Koza,et al.  Routine automated synthesis of five patented analog circuits using genetic programming , 2004, Soft Comput..

[15]  Jim Tørresen,et al.  A Scalable Approach to Evolvable Hardware , 2002, Genetic Programming and Evolvable Machines.

[16]  John R. Koza,et al.  Automatic Creation of Human-Competitive Programs and Controllers by Means of Genetic Programming , 2000, Genetic Programming and Evolvable Machines.

[17]  Takafumi Aoki,et al.  Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation , 2004, PPSN.

[18]  Dmitry Berenson,et al.  Hardware evolution of analog circuits for in-situ robotic fault-recovery , 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

[19]  Adrian Stoica,et al.  Evolvable Hardware System at Extreme Low Temperatures , 2005, ICES.

[20]  P. P. Chakrabarti,et al.  A synthesis system for analog circuits based on evolutionary search and topological reuse , 2005, IEEE Transactions on Evolutionary Computation.

[21]  Jianjun Hu,et al.  Open-ended robust design of analog filters using genetic programming , 2005, GECCO '05.

[22]  Geoffrey A. Hollinger,et al.  Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot , 2006, GECCO '06.

[23]  Licheng Jiao,et al.  Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm , 2006, Genetic Programming and Evolvable Machines.

[24]  Tatiana Kalganova,et al.  Constrained and Unconstrained evolution of " LCR" low-pass filters with oscillating length representation , 2006, IEEE Congress on Evolutionary Computation.

[25]  Vincenzo Cutello,et al.  Multi-Objective Evolutionary Algorithms and Pattern Search Methods for Circuit Design Problems , 2006, J. Univers. Comput. Sci..

[26]  Lei Chen,et al.  Automated Design Approach for Analog Circuit Using Genetic Algorithm , 2007, International Conference on Computational Science.

[27]  Giuseppe Nicosia,et al.  An Evolutionary Algorithm-Based Approach to Robust Analog Circuit Design using Constrained Multi-Objective Optimization , 2007, SGAI Conf..

[28]  Dario Floreano,et al.  Analog Genetic Encoding for the Evolution of Circuits and Networks , 2007, IEEE Transactions on Evolutionary Computation.

[29]  Kangshun Li,et al.  Automated analog circuit design using two-layer genetic programming , 2007, Appl. Math. Comput..

[30]  Giuseppe Nicosia,et al.  An Advanced Clonal Selection Algorithm with Ad-Hoc Network-Based Hypermutation Operators for Synthesis of Topology and Sizing of Analog Electrical Circuits , 2008, ICARIS.

[31]  Hod Lipson,et al.  Coevolution of Fitness Predictors , 2008, IEEE Transactions on Evolutionary Computation.